if we rely on the names of the submodules (sense_amp_array,
write_driver_array, etc.) for port_data's pins, we get into trouble on
multiport SRAMs. To avoid this we use explicit names for br/bl depending
on the port number in port_data. Now each submodule does no longer need to
figure out the right name depending on the port number.
Signed-off-by: Bastian Koppelmann <[email protected]>
Bastian Koppelmann
5e1f64c8f9