Jesse Cirimelli-Low 5cf50b333a bitcell array passing

2023-08-21 20:25:51 -07:00

..

__init__.py

Use packages for imports.

2022-07-13 15:55:57 -07:00

replica_bitcell_array.py

fixes to the custom module fix

2023-03-04 19:17:29 -08:00

sky130_bitcell_array.py

add nwell routing in bca

2023-08-21 20:12:36 -07:00

sky130_bitcell_base_array.py

bitcell array passing

2023-08-21 20:25:51 -07:00

sky130_bitcell.py

Update copyright year

2023-01-28 22:56:27 -08:00

sky130_capped_replica_bitcell_array.py

conform default behavior for sky130 custom modules to unit test

2023-06-07 17:31:12 -07:00

sky130_col_cap_array.py

Update copyright year

2023-01-28 22:56:27 -08:00

sky130_col_cap.py

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2023-01-28 22:56:27 -08:00

sky130_corner.py

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2023-01-28 22:56:27 -08:00

sky130_dummy_array.py

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2023-01-28 22:56:27 -08:00

sky130_dummy_bitcell.py

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2023-01-28 22:56:27 -08:00

sky130_internal.py

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2023-01-28 22:56:27 -08:00

sky130_replica_bitcell_array.py

fix single port by using existing custom modules

2023-03-03 14:17:57 -08:00

sky130_replica_bitcell.py

Update copyright year

2023-01-28 22:56:27 -08:00

sky130_replica_column.py

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2023-01-28 22:56:27 -08:00

sky130_row_cap_array.py

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2023-01-28 22:56:27 -08:00

sky130_row_cap.py

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2023-01-28 22:56:27 -08:00