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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-02 21:58:20 +02:00
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58da8af619689fb2002e2b03dbcd7eae0a859dd1
OpenRAM/technology/scn3me_subm/mag_lib
T
History
Matt Guthaus c63eb3be3b Fixed bug with missing tri gate via.
2018-01-29 17:29:30 -08:00
..
cell_6t.mag
Increase height slightlty to allow pnand3 to pass DRC.
2018-01-29 15:30:58 -08:00
ms_flop.mag
Add wells to fix DRC errors in SCMOS library cells.
2018-01-22 16:28:20 -08:00
replica_cell_6t.mag
Increase height slightlty to allow pnand3 to pass DRC.
2018-01-29 15:30:58 -08:00
sense_amp.mag
Fix devices sizes in SCMOS sense amp. Elaborate magic/netgen scripts in comments.
2018-01-24 13:02:55 -08:00
tri_gate.mag
Fixed bug with missing tri gate via.
2018-01-29 17:29:30 -08:00
write_driver.mag
Capitalize bitline labels in write driver
2018-01-24 13:15:14 -08:00
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