This website requires JavaScript.
Explore
Help
Sign In
luke
/
OpenRAM
Watch
1
Star
0
Fork
0
mirror of
https://github.com/VLSIDA/OpenRAM.git
synced
2026-08-29 01:24:39 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
58da8af619689fb2002e2b03dbcd7eae0a859dd1
OpenRAM
/
technology
T
History
Matt Guthaus
58da8af619
Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array.
2018-01-31 10:04:28 -08:00
..
freepdk45
Remove dead code ptx_port.
2018-01-19 16:19:05 -08:00
scn3me_subm
Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array.
2018-01-31 10:04:28 -08:00
setup_scripts
Remove spice model dir env variable for scn3me.
2018-01-30 10:54:29 -08:00