Matt Guthaus 58da8af619 Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array.

2018-01-31 10:04:28 -08:00

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cell_6t.gds

Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array.

2018-01-31 10:04:28 -08:00

ms_flop.gds

Add wells to fix DRC errors in SCMOS library cells.

2018-01-22 16:28:20 -08:00

replica_cell_6t.gds

Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array.

2018-01-31 10:04:28 -08:00

sense_amp.gds

Fix devices sizes in SCMOS sense amp. Elaborate magic/netgen scripts in comments.

2018-01-24 13:02:55 -08:00

tri_gate.gds

Fixed bug with missing tri gate via.

2018-01-29 17:29:30 -08:00

write_driver.gds

Capitalize bitline labels in write driver

2018-01-24 13:15:14 -08:00