mrg 54e4d147f6 Rail to ptx spacing based on routing layer not m1

2020-06-11 15:03:50 -07:00

..

pand2.py

Thin-cell decoder changes.

2020-05-29 10:36:07 -07:00

pand3.py

Vertical gates need both well contacts.

2020-05-13 16:54:35 -07:00

pbuf.py

Add no well option. Add stack gates vertical option.

2020-05-11 16:22:08 -07:00

pdriver.py

Thin-cell decoder changes.

2020-05-29 10:36:07 -07:00

pgate.py

Rail to ptx spacing based on routing layer not m1

2020-06-11 15:03:50 -07:00

pinv_dec.py

Thin-cell decoder changes.

2020-05-29 10:36:07 -07:00

pinv.py

Check min size inverter.

2020-05-13 16:54:26 -07:00

pinvbuf.py

Fix pinvbuf layers

2020-06-09 17:16:35 -07:00

pnand2.py

Incrase space for pnand gates

2020-06-09 16:34:15 -07:00

pnand3.py

More exact input spacing in pnand3

2020-06-10 16:19:24 -07:00

pnor2.py

Add no well option. Add stack gates vertical option.

2020-05-11 16:22:08 -07:00

precharge.py

Remove printf in precharge

2020-06-11 11:57:52 -07:00

ptristate_inv.py

Changes to simplify metal preferred directions and pitches.

2020-05-10 11:32:45 -07:00

ptx.py

Save LVS model with no u too for Calibre

2020-06-11 11:53:34 -07:00

pwrite_driver.py

Add boundary to all pgates

2020-04-21 15:21:57 -07:00

single_level_column_mux.py

Fix the bitline spacing in the column mux to a constant.

2020-06-03 15:47:03 -07:00

wordline_driver.py

Hard cells can accept height parameter too.

2020-06-01 16:46:00 -07:00