OpenRAM/compiler/router
Matt Guthaus 4ce6b040fd Debugging missing enclosures 2018-10-26 09:25:10 -07:00
..
tests Fix print check regression 2018-10-15 13:23:31 -07:00
direction.py Routing and connecting rails with vias done. 2018-09-07 14:46:58 -07:00
grid.py Supply router working except for off by one rail via error 2018-10-19 14:21:03 -07:00
grid_cell.py Supply router working except: 2018-09-18 12:57:39 -07:00
grid_path.py Convert supply tracks to sets for simpler algorithms. 2018-10-20 10:33:10 -07:00
grid_utils.py Fixed supply end-row via problem by restricting placement 2018-10-20 14:25:32 -07:00
pin_group.py Debugging missing enclosures 2018-10-26 09:25:10 -07:00
router.py Debugging missing enclosures 2018-10-26 09:25:10 -07:00
router_tech.py Refactor router to have pin_groups for pins and router_tech file 2018-10-25 13:36:35 -07:00
signal_grid.py Rewrote pin enclosure code to better address off grid pins. 2018-10-10 15:15:58 -07:00
signal_router.py Change non-preferred route costs. 2018-10-20 14:47:24 -07:00
supply_grid.py Supply router working except: 2018-09-18 12:57:39 -07:00
supply_router.py Debugging missing enclosures 2018-10-26 09:25:10 -07:00
vector3d.py Combine adjacent power supply pins finished 2018-10-25 14:25:52 -07:00