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OpenRAM/compiler/modules
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mrg 9b6eb4a120 Fix whitespace
2022-10-20 16:38:23 -07:00
..
__init__.py
sky130 rba passing :)
2022-09-12 16:07:00 -07:00
and2_dec.py
Use packages for imports.
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and3_dec.py
Use packages for imports.
2022-07-13 15:55:57 -07:00
and4_dec.py
Use packages for imports.
2022-07-13 15:55:57 -07:00
bank.py
Code format fixes
2022-08-13 13:58:53 -07:00
bitcell_1port.py
Move is_non_inverting graph code to bitcell_base class to work with pbitcell too.
2022-10-20 15:16:10 -07:00
bitcell_2port.py
Move is_non_inverting graph code to bitcell_base class to work with pbitcell too.
2022-10-20 15:16:10 -07:00
bitcell_array.py
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2022-07-13 15:55:57 -07:00
bitcell_base_array.py
Remove line ending whitespace
2022-07-22 19:52:38 +03:00
bitcell_base.py
Move is_non_inverting graph code to bitcell_base class to work with pbitcell too.
2022-10-20 15:16:10 -07:00
col_cap_array.py
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2022-07-13 15:55:57 -07:00
col_cap_bitcell_1port.py
Remove line ending whitespace
2022-07-22 19:52:38 +03:00
col_cap_bitcell_2port.py
Remove line ending whitespace
2022-07-22 19:52:38 +03:00
column_decoder.py
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2022-07-13 15:55:57 -07:00
column_mux_array.py
Remove line ending whitespace
2022-07-22 19:52:38 +03:00
column_mux.py
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2022-07-13 15:55:57 -07:00
control_logic_base.py
move most of place_instances to base
2022-08-01 10:33:48 -07:00
control_logic.py
move most of place_instances to base
2022-08-01 10:33:48 -07:00
delay_chain.py
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2022-07-13 15:55:57 -07:00
dff_array.py
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2022-07-13 15:55:57 -07:00
dff_buf_array.py
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2022-07-13 15:55:57 -07:00
dff_buf.py
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2022-07-13 15:55:57 -07:00
dff_inv_array.py
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2022-07-13 15:55:57 -07:00
dff_inv.py
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dff.py
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2022-07-13 15:55:57 -07:00
dummy_array.py
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2022-07-13 15:55:57 -07:00
dummy_bitcell_1port.py
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2022-07-13 15:55:57 -07:00
dummy_bitcell_2port.py
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2022-07-13 15:55:57 -07:00
dummy_pbitcell.py
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2022-07-13 15:55:57 -07:00
global_bitcell_array.py
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2022-07-13 15:55:57 -07:00
hierarchical_decoder.py
Remove line ending whitespace
2022-07-22 19:52:38 +03:00
hierarchical_predecode2x4.py
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hierarchical_predecode3x8.py
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2022-07-13 15:55:57 -07:00
hierarchical_predecode4x16.py
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2022-07-13 15:55:57 -07:00
hierarchical_predecode.py
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2022-07-13 15:55:57 -07:00
internal_base.py
Fix whitespace
2022-10-20 16:38:23 -07:00
inv_dec.py
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2022-07-13 15:55:57 -07:00
local_bitcell_array.py
Remove line ending whitespace
2022-07-22 19:52:38 +03:00
multibank.py
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2022-07-13 15:55:57 -07:00
nand2_dec.py
Remove line ending whitespace
2022-07-22 19:52:38 +03:00
nand3_dec.py
Remove line ending whitespace
2022-07-22 19:52:38 +03:00
nand4_dec.py
Remove line ending whitespace
2022-07-22 19:52:38 +03:00
orig_bitcell_array.py
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2022-07-13 15:55:57 -07:00
pand2.py
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2022-07-13 15:55:57 -07:00
pand3.py
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2022-07-13 15:55:57 -07:00
pand4.py
Use packages for imports.
2022-07-13 15:55:57 -07:00
pbitcell.py
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2022-07-13 15:55:57 -07:00
pbuf_dec.py
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2022-07-13 15:55:57 -07:00
pbuf.py
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2022-07-13 15:55:57 -07:00
pdriver.py
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2022-07-13 15:55:57 -07:00
pgate.py
Remove line ending whitespace
2022-07-22 19:52:38 +03:00
pinv_dec.py
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pinv.py
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2022-07-13 15:55:57 -07:00
pinvbuf.py
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2022-07-13 15:55:57 -07:00
pnand2.py
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2022-07-13 15:55:57 -07:00
pnand3.py
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2022-07-13 15:55:57 -07:00
pnand4.py
Remove line ending whitespace
2022-07-22 19:52:38 +03:00
pnor2.py
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2022-07-13 15:55:57 -07:00
port_address.py
Remove line ending whitespace
2022-07-22 19:52:38 +03:00
port_data.py
Fix typo on w_en
2022-08-04 16:35:09 -07:00
precharge_array.py
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2022-07-13 15:55:57 -07:00
precharge.py
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2022-07-13 15:55:57 -07:00
ptristate_inv.py
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2022-07-13 15:55:57 -07:00
ptx.py
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2022-07-13 15:55:57 -07:00
pwrite_driver.py
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2022-07-13 15:55:57 -07:00
replica_bitcell_1port.py
Remove line ending whitespace
2022-07-22 19:52:38 +03:00
replica_bitcell_2port.py
Remove line ending whitespace
2022-07-22 19:52:38 +03:00
replica_bitcell_array.py
Add fudge factor for bitcell array side rail spacings to fix DRC in freepdk45.
2022-07-20 10:27:30 -07:00
replica_column.py
Use packages for imports.
2022-07-13 15:55:57 -07:00
replica_pbitcell.py
Use packages for imports.
2022-07-13 15:55:57 -07:00
row_cap_array.py
Use packages for imports.
2022-07-13 15:55:57 -07:00
row_cap_bitcell_1port.py
Remove line ending whitespace
2022-07-22 19:52:38 +03:00
row_cap_bitcell_2port.py
Remove line ending whitespace
2022-07-22 19:52:38 +03:00
sense_amp_array.py
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2022-07-13 15:55:57 -07:00
sense_amp.py
Remove line ending whitespace
2022-07-22 19:52:38 +03:00
sram_1bank.py
remove references to bank_sel
2022-08-18 10:33:46 -07:00
sram_config.py
Write size updated in recompute_sizes
2022-08-10 15:36:41 -07:00
sram_multibank_template.v
Shrunk address register in multibank verilog
2022-07-28 15:03:41 -07:00
sram_multibank.py
Further fixes for new verilog naming convention
2022-08-18 11:03:13 -07:00
sram.py
Further fixes for new verilog naming convention
2022-08-18 11:03:13 -07:00
template.py
Code format fixes
2022-08-13 13:58:53 -07:00
tri_gate_array.py
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2022-07-13 15:55:57 -07:00
tri_gate.py
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2022-07-13 15:55:57 -07:00
wordline_buffer_array.py
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2022-07-13 15:55:57 -07:00
wordline_driver_array.py
Remove line ending whitespace
2022-07-22 19:52:38 +03:00
wordline_driver.py
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2022-07-13 15:55:57 -07:00
write_driver_array.py
Make sure num_wmasks is 0 when no wmask is generated
2022-08-10 16:35:39 -07:00
write_driver.py
Use packages for imports.
2022-07-13 15:55:57 -07:00
write_mask_and_array.py
Use packages for imports.
2022-07-13 15:55:57 -07:00