Matt Guthaus 45a53ed089 Rotate via in center for freepdk

2018-07-19 14:01:48 -07:00

..

base

Rotate via in center for freepdk

2018-07-19 14:01:48 -07:00

characterizer

Pass the sram design to lib instead of the sram wrapper

2018-07-18 11:51:42 -07:00

gdsMill

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

modules

Rotate via in center for freepdk

2018-07-19 14:01:48 -07:00

pgates

Remove uniqe pbitcell id since it isn't needed. Convert dos EOL to unix EOL characters. Convert python2.7 to python3 in pbitcell.

2018-06-29 11:49:02 -07:00

router

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tests

Pass the sram design to lib instead of the sram wrapper

2018-07-18 11:51:42 -07:00

verify

Add temporary options to LVS to allow name merging

2018-07-18 15:10:29 -07:00

debug.py

Output debug warnings and errors to stderr. Clean up regress script a bit.

2018-07-11 09:51:28 -07:00

example_config_freepdk45.py

Fix num words in example.

2018-02-23 12:17:43 -08:00

example_config_scn3me_subm.py

Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library.

2018-02-12 11:22:47 -08:00

gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

globals.py

Fix order of checkpointing so that it is done after characterizer and verify have found their executables.

2018-07-11 12:12:03 -07:00

Makefile

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openram.py

Improve openram output. Fix save output function name.

2018-07-12 10:35:38 -07:00

options.py

Fix options so it is in /tmp in RAM drive

2018-07-05 16:33:26 -07:00

sram_1bank.py

Use lower case names except for leaf cells and top level

2018-07-18 15:10:57 -07:00

sram_2bank.py

Add LVS correspondence points to each bank type

2018-07-18 14:29:04 -07:00

sram_4bank.py

Add LVS correspondence points to each bank type

2018-07-18 14:29:04 -07:00

sram_base.py

Add LVS correspondence points to each bank type

2018-07-18 14:29:04 -07:00

sram.py

Add verilog_write to sram wrapper for verilog unit test

2018-07-19 10:05:30 -07:00