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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 09:58:33 +02:00
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3f17679000c0be4f20ba330583e7f3a36bf26388
OpenRAM/compiler/router
T
History
Matt Guthaus 88f43cc754 Add the minimum pin enclosure that has DRC correct pin connections.
2018-10-24 16:41:33 -07:00
..
tests
Fix print check regression
2018-10-15 13:23:31 -07:00
direction.py
Routing and connecting rails with vias done.
2018-09-07 14:46:58 -07:00
grid_cell.py
Supply router working except:
2018-09-18 12:57:39 -07:00
grid_path.py
Convert supply tracks to sets for simpler algorithms.
2018-10-20 10:33:10 -07:00
grid_utils.py
Fixed supply end-row via problem by restricting placement
2018-10-20 14:25:32 -07:00
grid.py
Supply router working except for off by one rail via error
2018-10-19 14:21:03 -07:00
router.py
Add the minimum pin enclosure that has DRC correct pin connections.
2018-10-24 16:41:33 -07:00
signal_grid.py
Rewrote pin enclosure code to better address off grid pins.
2018-10-10 15:15:58 -07:00
signal_router.py
Change non-preferred route costs.
2018-10-20 14:47:24 -07:00
supply_grid.py
Supply router working except:
2018-09-18 12:57:39 -07:00
supply_router.py
Add the minimum pin enclosure that has DRC correct pin connections.
2018-10-24 16:41:33 -07:00
vector3d.py
DRC clean supply grid routing on control logic.
2018-09-20 16:00:13 -07:00
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