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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-01 18:48:10 +02:00
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3c3456596a4ed89076dfc2d6eebdf17d67efbc1d
OpenRAM/technology/scn4m_subm/sp_lib
T
History
mrg 3c3456596a Add replica row with dummy cells.
2019-06-14 14:38:55 -07:00
..
cell_1rw_1r.sp
Changed scmos bitcell 1rw,1r to have same tx widths as pbitcell.
2018-11-13 22:24:18 -08:00
cell_1w_1r.sp
Copy 1rw/1r cell to 1w/1r.
2019-02-24 09:54:45 -08:00
cell_6t.sp
Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd.
2018-11-05 10:59:08 -08:00
cell_6t.st0
Copy 1rw/1r cell to 1w/1r.
2019-02-24 09:54:45 -08:00
dff.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
dummy_cell_6t.sp
Add replica row with dummy cells.
2019-06-14 14:38:55 -07:00
replica_cell_1rw_1r.sp
Replaced bb layer with comment layer in 1rw,1r cell. Changed widths in replica cell.
2018-11-14 11:00:37 -08:00
replica_cell_1w_1r.sp
Copy 1rw/1r cell to 1w/1r.
2019-02-24 09:54:45 -08:00
replica_cell_6t.sp
Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd.
2018-11-05 10:59:08 -08:00
sense_amp.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
tri_gate.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
write_driver.sp
Replace write driver with human readable sp file.
2018-11-27 11:49:08 -08:00
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