Matt Guthaus 37c10a2198 Merge branch 'supply_routing' into dev

2018-12-07 17:04:37 -08:00

..

base

Fix instersection bug. Improve primary and secondary pin algo.

2018-12-04 16:53:04 -08:00

bitcells

Bitcell supply routing fixes.

2018-11-30 12:32:13 -08:00

characterizer

moved system call to datasheet.info generator

2018-12-05 17:35:35 -08:00

datasheet

removed outdated 'unknown' for analytical frequency

2018-12-06 10:29:48 -08:00

drc

Moving wide metal spacing to routing grid level

2018-10-15 09:59:16 -07:00

gdsMill

Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.

2018-11-16 11:48:41 -08:00

modules

Bitcell supply routing fixes.

2018-11-30 12:32:13 -08:00

pgates

Passed freepdk45 tests with pdriver.py

2018-12-07 12:58:05 -08:00

router

Added router timing code. Commented combine adjacent pins due to run-time complexity

2018-12-07 13:54:18 -08:00

tests

Skip pdriver test until LVS fix

2018-12-07 07:41:35 -08:00

verify

Remove redundant DRC run in magic.

2018-11-05 13:30:42 -08:00

debug.py

Output debug warnings and errors to stderr. Clean up regress script a bit.

2018-07-11 09:51:28 -07:00

example_config_freepdk45.py

Remove options from example config files

2018-11-05 12:47:47 -08:00

example_config_scn4m_subm.py

Revert to 5V example until we fix spice models in scn4m_subm

2018-11-27 14:17:06 -08:00

gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

git_id

track git_id

2018-12-05 16:13:52 -08:00

globals.py

Only print_time when not a unit test or debug_level set

2018-12-07 15:14:28 -08:00

Makefile

Clean up Makefile for unit tests

2018-12-05 12:58:10 -08:00

openram.py

Print start time after banner and init

2018-12-07 15:50:18 -08:00

options.py

Simplifying supply router to single grid track

2018-12-04 08:41:57 -08:00

profile_stats.py

Add profile scripts

2018-12-07 08:56:40 -08:00

run_profile.sh

Add profile scripts

2018-12-07 08:56:40 -08:00

sram_1bank.py

Remove extraneous m2m3 via that causes DRC

2018-12-06 12:45:45 -08:00

sram_2bank.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00

sram_base.py

Change Netlisting to submodules to reflect what time is of

2018-12-06 11:59:20 -08:00

sram_config.py

Increase size for warning of column mux limit

2018-12-06 13:57:38 -08:00

sram.py

Merge branch 'dev' into datasheet_gen

2018-12-07 04:29:07 -08:00

view_profile.py

Add profile scripts

2018-12-07 08:56:40 -08:00