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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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304971ff6086982d14a638439dd5407ba3da56ab
OpenRAM/compiler/pgates
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mrg 304971ff60 Fix ptx so nmos and pmos have same active offset and gates align
2020-02-04 17:38:35 +00:00
..
pand2.py
Clean up and generalize layer rules.
2019-12-17 11:03:36 -08:00
pand3.py
Clean up and generalize layer rules.
2019-12-17 11:03:36 -08:00
pbuf.py
Clean up and generalize layer rules.
2019-12-17 11:03:36 -08:00
pdriver.py
Clean up and generalize layer rules.
2019-12-17 11:03:36 -08:00
pgate.py
Fix ptx so nmos and pmos have same active offset and gates align
2020-02-04 17:38:35 +00:00
pinv.py
Cleanup and rename vias.
2020-01-30 01:45:33 +00:00
pinvbuf.py
Clean up and generalize layer rules.
2019-12-17 11:03:36 -08:00
pnand2.py
Cleanup and rename vias.
2020-01-30 01:45:33 +00:00
pnand3.py
Cleanup and rename vias.
2020-01-30 01:45:33 +00:00
pnor2.py
Cleanup and rename vias.
2020-01-30 01:45:33 +00:00
precharge.py
Cleanup and rename vias.
2020-01-30 01:45:33 +00:00
ptristate_inv.py
Cleanup and rename vias.
2020-01-30 01:45:33 +00:00
ptx.py
Fix ptx so nmos and pmos have same active offset and gates align
2020-02-04 17:38:35 +00:00
pwrite_driver.py
Add separate well design rules.
2020-01-23 19:43:41 +00:00
single_level_column_mux.py
modules: Use add_power_pin API for all modules
2020-01-28 11:47:49 +01:00
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