OpenRAM/compiler/characterizer
Hunter Nichols cc5b347f42 Added analyical model test which compares measured delay to model delay. 2019-04-03 16:26:20 -07:00
..
__init__.py Merge branch 'dev' into multiport_characterization 2019-01-15 16:33:39 -08:00
bitline_delay.py Added slews measurements to the model checker. Removed unused code in bitline delay class. 2019-01-09 22:42:34 -08:00
charutils.py Added data parsing to measurement objects and adding power measurements. 2018-12-20 15:54:56 -08:00
delay.py Added analyical model test which compares measured delay to model delay. 2019-04-03 16:26:20 -07:00
functional.py Moved feasible period search from functional.py to tests. 2018-12-05 23:23:40 -08:00
lib.py Added lib test which generates multiple corner models. Only does process currently. 2019-03-04 16:27:10 -08:00
logical_effort.py Added analyical model test which compares measured delay to model delay. 2019-04-03 16:26:20 -07:00
measurements.py Fix bitline measurement delays and adjusted default delay chain for column mux srams 2019-02-06 00:46:25 -08:00
model_check.py Added additions to account for custom delay chains. 2019-03-28 17:16:23 -07:00
setup_hold.py Updating ms_flop removal. 2018-09-13 11:40:24 -07:00
simulation.py Functional simulation uses threshold for high and low noise margins 2018-11-28 16:55:04 -08:00
stimuli.py Added tracking for available data. 2019-02-12 16:28:37 -08:00
trim_spice.py Added bitline measures with hardcoded names. 2018-12-12 00:43:08 -08:00
worst_case.py Made delay.py a child of simulation.py. Removed duplicate code in delay and changed some in simulation 2018-10-09 17:44:28 -07:00