mrg 120c4de5ad Fix placement of delay chain to align with control logic rows.

2021-05-05 14:21:53 -07:00

..

base

Must transitively cut blockages until no more.

2021-05-05 13:44:06 -07:00

bitcells

Update copyright year.

2021-01-22 11:23:28 -08:00

characterizer

Removed measurement check which conflicts with multiport memories

2021-04-21 15:53:27 -07:00

custom

Add noninverting logic function to custom decoder cells.

2021-04-22 16:13:54 -07:00

datasheet

Merge branch 'dev' into automated_analytical_model

2021-02-01 01:49:45 -08:00

drc

Update copyright year.

2021-01-22 11:23:28 -08:00

example_configs

Add vdd/gnd pins to the side.

2021-05-03 15:14:15 -07:00

gdsMill

Add error with zero length labels on GDS write.

2021-05-05 13:44:31 -07:00

modules

Fix placement of delay chain to align with control logic rows.

2021-05-05 14:21:53 -07:00

pgates

Add wells to driver stages. Remove unnecessary height/center in control logic.

2021-03-25 10:00:24 -07:00

router

Add left stripe power routes to tree router as option.

2021-05-05 13:45:12 -07:00

sram

Default supply routing is tree.

2021-05-05 14:04:24 -07:00

tests

Update unit test results with new Verilog models.

2021-04-15 15:48:20 -07:00

verify

Remove option that causes errors and is unused.

2021-03-01 16:36:27 -08:00

debug.py

Skywater changes.

2021-03-22 15:48:14 -07:00

gen_stimulus.py

Update copyright year.

2021-01-22 11:23:28 -08:00

globals.py

Specify ImportError to see other errors

2021-04-22 16:13:32 -07:00

Makefile

…

openram.py

Update copyright year.

2021-01-22 11:23:28 -08:00

options.py

Abstracted LEF added. Params for array wordline layers.

2021-04-21 11:04:01 -07:00

printGDS.py

Add printGDS script to aid debugging things.

2020-12-02 11:52:38 -08:00

processGDS.py

Make default no magnification to text. PEP8 Cleanup

2020-12-09 11:42:28 -08:00

run_profile.sh

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sram_factory.py

Update copyright year.

2021-01-22 11:23:28 -08:00

view_profile.py

Update copyright year.

2021-01-22 11:23:28 -08:00