| .. |
|
and2_dec.py
|
Changed names of some functions in base CACTI delay function. Removed unused analytical delay functions.
|
2021-07-12 13:02:22 -07:00 |
|
and3_dec.py
|
Changed names of some functions in base CACTI delay function. Removed unused analytical delay functions.
|
2021-07-12 13:02:22 -07:00 |
|
and4_dec.py
|
Changed names of some functions in base CACTI delay function. Removed unused analytical delay functions.
|
2021-07-12 13:02:22 -07:00 |
|
bank.py
|
fix vnb and vpb routing in rba
|
2021-07-08 18:31:55 -07:00 |
|
bank_select.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
bitcell_array.py
|
Add hierarchical seperator option to work with Xyce measurements.
|
2021-05-14 16:16:25 -07:00 |
|
bitcell_base_array.py
|
don't copy pwell pin onto nwell
|
2021-07-01 15:19:59 -07:00 |
|
col_cap_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
column_mux_array.py
|
Added a graph exclusion clear for the mux to prevent previous graph creations causing bugs.
|
2021-06-14 14:39:54 -07:00 |
|
control_logic.py
|
Fix placement of delay chain to align with control logic rows.
|
2021-05-05 14:21:53 -07:00 |
|
delay_chain.py
|
Fix Verilog module typo. Adjust RBL route.
|
2021-05-06 14:32:47 -07:00 |
|
dff_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
dff_buf.py
|
spacing must be two extensions (one for each cell)
|
2021-06-04 08:56:06 -07:00 |
|
dff_buf_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
dff_inv.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
dff_inv_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
dummy_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
global_bitcell_array.py
|
Changed bitcell exclusion to instead exclude array instances to prevent issues of module exclusion affecting other modules.
|
2021-06-21 17:20:25 -07:00 |
|
hierarchical_decoder.py
|
Use local spacing rule
|
2021-06-16 18:41:39 -07:00 |
|
hierarchical_predecode.py
|
remove print statement
|
2021-06-17 03:23:46 -07:00 |
|
hierarchical_predecode2x4.py
|
Skywater changes.
|
2021-03-22 15:48:14 -07:00 |
|
hierarchical_predecode3x8.py
|
Skywater changes.
|
2021-03-22 15:48:14 -07:00 |
|
hierarchical_predecode4x16.py
|
Skywater changes.
|
2021-03-22 15:48:14 -07:00 |
|
local_bitcell_array.py
|
Add hierarchical seperator option to work with Xyce measurements.
|
2021-05-14 16:16:25 -07:00 |
|
module_type.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
multibank.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
orig_bitcell_array.py
|
Add hierarchical seperator option to work with Xyce measurements.
|
2021-05-14 16:16:25 -07:00 |
|
port_address.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
port_data.py
|
Merged with dev, addressed conflict in port data
|
2021-06-21 17:23:32 -07:00 |
|
precharge_array.py
|
support multi cell wide precharge cells
|
2021-04-23 22:49:29 -07:00 |
|
replica_bitcell_array.py
|
merge in dev
|
2021-05-28 14:06:23 -07:00 |
|
replica_column.py
|
When determining bitline names, added a technology check for sky130.
|
2021-06-16 17:04:02 -07:00 |
|
row_cap_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
sense_amp_array.py
|
use consistent amp spacing
|
2021-05-07 11:29:43 -07:00 |
|
tri_gate_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
wordline_buffer_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
wordline_driver_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
write_driver_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
write_mask_and_array.py
|
Add via when write driver supply is different layer
|
2021-04-28 15:16:26 -07:00 |
1e08005639