mirror of https://github.com/VLSIDA/OpenRAM.git
68 lines
3.6 KiB
Markdown
68 lines
3.6 KiB
Markdown
### [Go Back](./index.md#table-of-contents)
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# Results
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This page of the documentation explains the results of OpenRAM.
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## Table of Contents
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1. [Small Layouts](#small-layouts)
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1. [Relative Planar Bitcells](#relative-planar-bitcells-035um-scmos)
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1. [SRAM Area](#sram-area)
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1. [Generated Layout by OpenRAM](#generated-layout-by-openram-for-a-multiport-6r2w-sram-in-32-nm-soi-cmos-technology)
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1. [Timing and Density Results for Generated SRAMs](#timing-and-density-results-for-generated-srams)
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1. [Comparison with Fabricated SRAMs](#comparison-with-fabricated-srams)
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1. [Conclusions](#conclusions)
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## Small Layouts
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| <img width="320" src="../assets/images/results/small_layouts_1.png"> | <img width="320" src="../assets/images/results/small_layouts_2.png"> |
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| :----------------------------------------------------------: | :----------------------------------------------------------: |
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| 512 x 16b x 1rw FreePDK45 | 2048 x 32b x 1rw FreePDK45 |
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## Relative Planar Bitcells (0.35um SCMOS)
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| <img height="184" src="../assets/images/bitcells/6t.png"> | <img height="278" src="../assets/images/bitcells/10t.png"> | <img height="424" src="../assets/images/bitcells/dff.png"> |
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| :-----------------------------------------------: | :------------------------------------------------: | :--------------------------------------------------: |
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| Standard 6T (1rw) 6.8um x 9.2um | Isolated Read 10T (1rw, 1r) 10.9um x 13.9um | DFF 21.9um x 21.2um (from OSU standard cell library) |
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## SRAM Area
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## Generated Layout by OpenRAM for a multiport (6R/2W) SRAM in 32 nm SOI CMOS Technology
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## Timing and Density Results for Generated SRAMs
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## Comparison with Fabricated SRAMs
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| $\textrm{Reference}$ | $\textrm{Feature Size}$ | $\textrm{Technology}$ | $\textrm{Density } (Mb/mm^2)$ |
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| :---------------------- | :---------------------: | :-------------------: | :---------------------------: |
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| $\textrm{IEEE-VLSI'08}$ | $65 nm$ | $\textrm{CMOS}$ | $0.7700$ |
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| $\textrm{JSSC'11}$ | $45 nm$ | $\textrm{CMOS}$ | $0.3300$ |
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| $\textrm{JSSC'13}$ | $40 nm$ | $\textrm{CMOS}$ | $0.9400$ |
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| $\textrm{OpenRAM}$ | $45 nm$ | $\textrm{FreePDK45}$ | $0.8260$ |
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| $\textrm{JSSC'92}$ | $0.5 \mu m$ | $\textrm{CMOS}$ | $0.0036$ |
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| $\textrm{JSSC'94}$ | $0.5 \mu m$ | $\textrm{BICMOS}$ | $0.0020$ |
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| $\textrm{JSSC'99}$ | $0.5 \mu m$ | $\textrm{CMOS}$ | $0.0050$ |
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| $\textrm{OpenRAM}$ | $0.5 \mu m$ | $\textrm{SCMOS}$ | $0.0050$ |
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## Conclusions
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* The main motivation behind OpenRAM is to promote and simplify memory-related research in academia and provides a platform to implement and test new memory designs.
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* OpenRAM is open-sourced, flexible, and portable and can be adapted to various technologies.
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* OpenRAM generates the circuit, functional model, and layout of variable-sized SRAMs.
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* OpenRAM provides a memory characterizer for synthesis timing/power models.
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* We are also actively introducing new features, such as non-6T memories, variability characterization, word-line segmenting, characterization speed-up, etc.
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