12 Commits

Author	SHA1	Message	Date
Hunter Nichols	0e96648211	Added linear corner factors in analytical delay model.	2019-03-04 00:42:18 -08:00
Matt Guthaus	091b4e4c62	Add size commments to spize. Change pdriver stage effort.	2019-01-23 17:27:15 -08:00
Matt Guthaus	b58fd03083	Change pbuf/pinv to pdriver in control logic.	2019-01-23 12:03:52 -08:00
Matt Guthaus	a418431a42	First draft of sram_factory code	2019-01-16 16:15:38 -08:00
Hunter Nichols	ea55bda493	Changed s_en delay calculation based recent control logic changes.	2018-12-05 17:10:11 -08:00
Hunter Nichols	722bc907c4	Merged with dev. Fixed conflicts in tests.	2018-12-02 23:09:00 -08:00
Matt Guthaus	2ed8fc1506	pgate inputs and outputs are all on M1 for flexible via placement when using gates.	2018-11-28 12:42:29 -08:00
Matt Guthaus	9e0b31d685	Make pand2 and pbuf derive pgate. Initial DRC wrong layout.	2018-11-26 16:19:18 -08:00
Matt Guthaus	b440031855	Add netlist only mode to new pgates	2018-11-26 15:29:42 -08:00
Jennifer Eve Sowash	bb7773ca7f	Editted pbuf.py to pass regression.	2018-11-20 14:39:11 -08:00
Jennifer Sowash	b6f1409fb9	Testing to ensure branch is up to date with dev. Added 04_pbuf_test.py and made changes to pbuf.py to align with comments.	2018-11-12 13:24:27 -08:00
Jennifer Sowash	82abd32785	Added pbuf.py to create a single buffer.	2018-11-12 09:53:21 -08:00