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OpenRAM
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2,850 Commits 4 Branches 63 Tags 78 MiB
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4 Commits

Author SHA1 Message Date
mrg 22c821f5d8 Change port_address test to 256 for riscv 2020-06-23 15:40:00 -07:00
mrg 5514996708 Auto-generate port dependent cell names. 2020-06-05 15:09:22 -07:00
mrg 2fcecb7227 Variable zjog. 512 port address test. s8 port address working. 2020-06-04 16:01:32 -07:00
mrg e93f3f1d2e Add 1rw_1r tests 2020-06-03 14:30:15 -07:00