Hunter Nichols
10085d85ab
Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files.
2021-07-21 14:59:02 -07:00
Hunter Nichols
1acc10e9d5
Added name changes to on resistance params. Added input capacitance functions to relevant modules for CACTI input load functions.
2021-07-21 12:24:08 -07:00
Hunter Nichols
2c9f755a73
Added on resistance functions for pgates, custom cells, and bitcell.
2021-07-12 14:25:37 -07:00
mrg
467aaa708d
Add noninverting logic function to custom decoder cells.
2021-04-22 16:13:54 -07:00
Matt Guthaus
30fc81a1f0
Update copyright year.
2021-01-22 11:23:28 -08:00
mrg
e4bc2c4914
Update property settings with getters/setters
2020-11-14 08:08:42 -08:00
mrg
8021430122
Fix pbitcell erros
2020-11-13 15:55:55 -08:00
mrg
1890385be1
Use custom cells when needed.
2020-11-03 11:58:25 -08:00
mrg
da721a677d
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
mrg
fa89b73ef8
PR from mithro + other changable GDS file names
2020-11-02 16:00:16 -08:00
mrg
b3b03d4d39
Hard cells can accept height parameter too.
2020-06-01 16:46:00 -07:00
mrg
4a67f7dc71
Thin-cell decoder changes.
...
Add hard decoder gates (nand, inv, pnan)
Add conditions for routing using LI layer in s8.
Generalize bus layers for decoders.
Move custom cells to own directory.
Fixed via directions, etc.
Add 4x16 hierarchical decoder and test case
2020-05-29 10:36:07 -07:00