9 Commits

Author	SHA1	Message	Date
mrg	0c3ee643ab	Remove add_mod and add module whenever calling add_inst.	2021-11-22 11:33:27 -08:00
Hunter Nichols	10085d85ab	Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files.	2021-07-21 14:59:02 -07:00
Hunter Nichols	1acc10e9d5	Added name changes to on resistance params. Added input capacitance functions to relevant modules for CACTI input load functions.	2021-07-21 12:24:08 -07:00
Hunter Nichols	2c9f755a73	Added on resistance functions for pgates, custom cells, and bitcell.	2021-07-12 14:25:37 -07:00
Matt Guthaus	30fc81a1f0	Update copyright year.	2021-01-22 11:23:28 -08:00
mrg	da721a677d	Remove EOL whitespace globally	2020-11-03 06:29:17 -08:00
mrg	acfec369d6	Add ptx cell properties	2020-10-28 09:54:15 -07:00
mrg	4a58f09c1c	Use 4x16 decoder with dual port bitcell in tests.	2020-10-05 10:52:56 -07:00
mrg	1fc4040607	Add pand4 and pnand4	2020-10-02 14:54:12 -07:00