16 Commits

Author	SHA1	Message	Date
mrg	493c9125f1	Read different modules overrides for different num ports	2020-11-06 11:09:50 -08:00
mrg	da721a677d	Remove EOL whitespace globally	2020-11-03 06:29:17 -08:00
mrg	ae0f4fe682	Fix spice model bin parameter error	2020-10-28 10:39:54 -07:00
mrg	acfec369d6	Add ptx cell properties	2020-10-28 09:54:15 -07:00
jcirimel	854d51c721	merge dev	2020-08-19 14:25:41 -07:00
jcirimel	e7c9914d77	decoder passing except for bus route	2020-08-13 16:20:39 -07:00
mrg	5fc6438553	Fix pinv_dec super call	2020-08-12 13:22:28 -07:00
mrg	30976df48f	Change inheritance inits to use super	2020-08-06 11:33:26 -07:00
mrg	c7bc01c3a9	Clean up binning. Fix mults to 1 for certain gates.	2020-07-15 17:15:42 -07:00
mrg	2b7d89d2c1	Fix netlist_only in sky130	2020-07-13 14:59:31 -07:00
jcirimel	59562f2b92	move accuracy_requirement from techfile to config	2020-06-25 06:44:07 -07:00
mrg	6e0008403e	Update new tech name	2020-06-15 10:06:17 -07:00
mrg	91f20f2cf6	Better centering of pinv_dec	2020-06-14 14:09:45 -07:00
mrg	33a32101c9	DRC and LVS fixes for pinv_dec	2020-06-12 15:23:51 -07:00
mrg	443b8fbe23	Change s8 to sky130	2020-06-12 14:23:26 -07:00
mrg	4a67f7dc71	Thin-cell decoder changes. ... Add hard decoder gates (nand, inv, pnan) Add conditions for routing using LI layer in s8. Generalize bus layers for decoders. Move custom cells to own directory. Fixed via directions, etc. Add 4x16 hierarchical decoder and test case	2020-05-29 10:36:07 -07:00