4 Commits

Author	SHA1	Message	Date
jcirimel	1e7ae06b7e	fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end	2020-10-08 05:32:03 -07:00
jcirimel	d40c3588ed	no wl for col end	2020-10-08 03:34:16 -07:00
jcirimel	888646cdf9	merge in wlbuf and begin work on 32kb memory	2020-10-06 05:03:59 -07:00
jcirimel	5246d0a93b	track s8 customs modules	2020-10-05 12:10:44 -07:00