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OpenRAM
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4,968 Commits 5 Branches 63 Tags 79 MiB
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10 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low 88241ca685 add fix for cypress sp wls 2026-04-28 17:19:54 -07:00
Jesse Cirimelli-Low cb7f117daa squash commits 2026-04-22 01:33:47 -07:00
Jesse Cirimelli-Low 53d53ec271 checkpoint from tt submission 2026-01-14 12:08:26 -08:00
Jesse Cirimelli-Low d7c3bbea3e crba passing again norbl/leftrbl 2023-10-28 18:05:07 -07:00
Jesse Cirimelli-Low 8794070ebc various refactor changes 2023-08-28 12:31:55 -07:00
Jesse Cirimelli-Low ba51149dce placement working for sp capped rba, need fix rowcap patterns 2023-08-26 18:54:07 -07:00
Eren Dogan e5fc25da6f Update copyright year 2023-01-28 22:56:27 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00