OpenRAM

Author	SHA1	Message	Date
mrg	b9d993c88b	Add dummy bitcell module. Modify bitcell logic to guess if bitcell is not "bitcell" No longer need to specify replica (and dummy) bitcell explicitly Add support for 1 or 2 port replica array.	2019-07-05 12:58:52 -07:00
mrg	dd62269e0b	Some cleanup	2019-07-05 08:18:58 -07:00
mrg	8b0b2e2817	Merge branch 'dev' into rbl_revamp	2019-07-03 14:05:28 -07:00
mrg	70c83f20b6	Fixes to pass unit tests. Skip replica tests until freepdk45 cells are made. Revert to previous control and row addr dff placement.	2019-07-03 13:37:56 -07:00
mrg	bc4a3ee2b7	New port_data module works in SCMOS	2019-07-03 13:17:12 -07:00
Hunter Nichols	3f5b60856a	Fixed key error with analytical delay of write ports.	2019-06-28 13:49:04 -07:00
Hunter Nichols	4e08e2da87	Merged and fixed conflicts with dev	2019-06-25 16:55:50 -07:00
Matt Guthaus	6e044b776f	Merge branch 'pep8_cleanup' into dev	2019-06-14 08:47:10 -07:00
mrg	58f51b72f1	Merge fixes	2019-06-03 15:31:49 -07:00
mrg	bd4d965e37	Begin single layer supply router	2019-06-03 15:27:37 -07:00
mrg	4612c9c182	Move power pins before no route option	2019-06-03 15:27:37 -07:00
mrg	bf86969972	Create sram subdirectory.	2019-05-31 08:56:24 -07:00