58 Commits

Author	SHA1	Message	Date
Hunter Nichols	b8061d3a4e	Added initial code for determining the logical effort delay of the wordline.	2018-11-08 23:54:18 -08:00
Hunter Nichols	e5dcf5d5b1	Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass.	2018-10-30 22:19:26 -07:00
Hunter Nichols	016604f846	Fixed spacing in golden lib files. Added column mux into analytical model.	2018-10-24 00:16:26 -07:00
Matt Guthaus	4bf1e206e2	Merge branch 'dev' into supply_routing	2018-10-17 09:47:18 -07:00
Michael Timothy Grimes	e60deddfea	adding 6T transistor size parameters to tech files for use in pbitcell.	2018-10-17 07:28:56 -07:00
Matt Guthaus	4932d83afc	Add design rules classes for complex design rules	2018-10-12 09:44:36 -07:00
Matt Guthaus	f4389bdd8f	Add extra track spacings in some routes.	2018-09-13 14:12:24 -07:00
Matt Guthaus	63d0523228	Added scn4m_subm. ... Added scn4m_subm files (instead of scn4me_subm). Fixed missing cifoutput/cifinput in magic tech file and gds files. Fixed incorrect M3/via3/M4 design rules.	2018-09-13 12:53:35 -07:00