OpenRAM

Commit Graph

Author	SHA1	Message	Date
Michael Timothy Grimes	fc5f163828	Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport	2018-09-18 18:56:15 -07:00
Michael Timothy Grimes	9acc8a9532	Altering multiport checks across several unit tests.	2018-09-13 18:49:20 -07:00
Matt Guthaus	3539887ee4	Updating ms_flop removal. Updated characterizer for dff. Added new setup/hold results for dff instead of ms_flop. Removed ms_flop references in sram-base. Fixed syntax errors in SCN3ME tech file.	2018-09-13 11:40:24 -07:00
Michael Timothy Grimes	586c72e4f7	Altering certain tests to include multiport checks.	2018-09-09 22:08:03 -07:00
Matt Guthaus	6963a1092f	Make bitcell width/height not static. Update modules to use it for pbitcell.	2018-09-04 11:55:22 -07:00
Matt Guthaus	de6f22aa3c	Fix unit test permissions	2018-09-04 10:48:37 -07:00
Michael Timothy Grimes	af0756382f	Merging changes and updating multiport syntax across several tests	2018-09-03 19:36:20 -07:00
Michael Timothy Grimes	774c14ad75	changing 19_psingle_bank_test to test layout for a single bank using pbitcell with 1 RW port (equivalent to using 6T cell)	2018-09-03 17:47:29 -07:00
Matt Guthaus	563ff77d44	Add sram_config class. Rename port variables for better description.	2018-08-31 12:03:28 -07:00
Matt Guthaus	8752d799b4	Skip pbitcell tests for now	2018-08-28 10:45:50 -07:00
Matt Guthaus	ac8a16ebdf	Fix permissions for unit tests to be run standalone.	2018-08-28 10:31:58 -07:00
Michael Timothy Grimes	e147f807a5	adding a unit test for multiported bank, this test will skip in the regression testing because multiported bank does not pass drc yet	2018-08-15 04:32:56 -07:00

12 Commits