OpenRAM

Commit Graph

Author	SHA1	Message	Date
Matt Guthaus	93e830e800	Add new supplies to replica bitline	2018-07-16 10:49:43 -07:00
Matt Guthaus	94db2052dd	Consolidate metal pitch rules to new design class	2018-07-09 15:42:46 -07:00
Matt Guthaus	f34c4eb7dc	Convert entire OpenRAM to use python3. Works with Python 3.6. Major changes: Remove mpmath library and use numpy instead. Convert bytes to new bytearrays. Fix class name check for duplicate gds instances. Add explicit integer conversion from floats. Fix importlib reload from importlib library Fix new key/index syntax issues. Fix filter and map conversion to lists. Fix deprecation warnings. Fix Circuits vs Netlist in Magic LVS results. Fix file closing warnings.	2018-05-14 16:15:45 -07:00
Matt Guthaus	0e35937da5	Commit local changes. Forgot what the status is.	2018-05-11 09:15:29 -07:00
Matt Guthaus	97c08bce95	Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control. Shift s_en buffers even with other cells.	2018-03-23 08:14:09 -07:00
Matt Guthaus	b867e163a6	Move label pins to center like layout pins. Rework of control logic with vertical poly. Passes DRC/LVS. Single bank passing DRC.	2018-03-23 08:12:59 -07:00
Matt Guthaus	8ca9ba4244	Recreate delay chain and RBL to have vertical poly only.	2018-03-23 08:12:47 -07:00
Matt Guthaus	0c203c1c7e	RBL width is max of delay chain or bitcell load.	2018-03-05 10:23:13 -08:00
mguthaus	28fe49d069	Change RBL to allow stages and FO for configuration	2018-02-16 11:51:01 -08:00
Matt Guthaus	7100d6f904	Organize top-level files into subdirs.	2018-02-09 10:25:24 -08:00

10 Commits