11 Commits

Author	SHA1	Message	Date
Matt Guthaus	5e0eb609da	Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.	2018-11-16 11:48:41 -08:00
Matt Guthaus	a094db9077	Merge branch 'multiport' into supply_routing	2018-10-11 09:56:38 -07:00
Matt Guthaus	e22e658090	Converted all submodules to use _bit notation instead of [bit]	2018-10-11 09:53:08 -07:00
Matt Guthaus	bb83e5f1be	Move clk up in dff arrays for supply pin access	2018-10-05 08:18:38 -07:00
Matt Guthaus	e17c69be3e	Clean up new code for add_modules, add_pins and netlist/layouts.	2018-08-28 10:24:09 -07:00
Matt Guthaus	6401cbf2a6	Move place function to instance class rather than hierarchy.	2018-08-27 17:25:39 -07:00
Matt Guthaus	8664f7a0b8	Converted all modules to not run create_layout when netlist_only ... mode is enabled.	2018-08-27 16:42:48 -07:00
Matt Guthaus	138a70fc23	Add place_inst routine. ... Separate create netlist and layout in some modules.	2018-08-27 10:42:40 -07:00
Matt Guthaus	f43d4cc98f	Fix routing clk connections of dff arrays	2018-07-18 11:38:58 -07:00
Matt Guthaus	873be38e15	Add M3 pins on dff_buf array	2018-04-11 12:09:15 -07:00
Matt Guthaus	ed8eaed54f	Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.	2018-03-23 08:12:47 -07:00