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OpenRAM
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3190 Commits

Author SHA1 Message Date
Matt Guthaus 347f1f97fd Merge branch 'master' into magic_netgen_support 2017-11-15 17:05:38 -08:00
mguthaus 2eb9f5c6bc Move verify into a module. Make characterizer a module. Move exe searching to modules. 2017-11-15 17:02:53 -08:00
Matt Guthaus 658f794b12 Add draft of assura DRC/LVS 2017-11-15 12:07:10 -08:00
Matt Guthaus f6410e0371 Merge branch 'master' into dev 2017-11-15 11:46:11 -08:00
Matt Guthaus 75a3884568 Remove tab 2017-11-15 11:45:55 -08:00
Matt Guthaus 88678d9fa4 Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev 2017-11-15 07:45:38 -08:00
Matt Guthaus f123a3ca40 Merge branch 'master' into dev 2017-11-15 07:43:56 -08:00
Matt Guthaus 102db4fecf Fixed prune unit test by relaxing tolerance. 2017-11-15 07:43:43 -08:00
Matt Guthaus a7a9abbde6 Fix new paragraph in CONTRIBUTING itemized list. 2017-11-14 17:17:21 -08:00
Matt Guthaus 37edd7cac6 Change unit tests to use verify instead of calibre. Debugging gds read comments in magic.py. 2017-11-14 16:24:26 -08:00
Matt Guthaus 4285e576f8 Change error to warning for magic/netgen. 2017-11-14 15:49:47 -08:00
Matt Guthaus 40410cc9f5 Clean up code to work when no drc/lvs/pex is found. 2017-11-14 15:31:58 -08:00
Matt Guthaus 257cd62d25 Remove tools from tech file and have search order preference like spice. 2017-11-14 15:27:03 -08:00
Matt Guthaus 3e0f39cd8e Skeleton code for indirect DRC/LVS/PEX tools. 2017-11-14 14:59:14 -08:00
Matt Guthaus 70ab672c5c Pad strings in GDS to even number of bytes per bug report. 2017-11-14 14:30:00 -08:00
Matt Guthaus 29c5ab48f0 Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output. 2017-11-14 13:24:14 -08:00
Matt Guthaus e818cdc992 Update README for xa 2017-11-12 10:56:37 -08:00
Matt Guthaus 8071dcc0f3 Add customsim (xa) as optional simulator. Fix regex to support scientific notation. Go through list of preferred simulators in order. Always abort if command-line simulator not found. 2017-11-12 10:42:41 -08:00
Jun Chen 054e4d3c28 my change 2017-11-11 16:54:04 +09:00
Matt Guthaus a34a9ecb47 Separate the contributing file from the README to follow GitHub recommendations. 2017-11-09 13:24:42 -08:00
Matt Guthaus 93e24c4651 More formatting for README.md 2017-11-09 11:24:42 -08:00
Matt Guthaus 4e3f90cbcd Format fixes to README.md 2017-11-09 11:22:14 -08:00
Matt Guthaus 95f1a24f72 Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
Matt Guthaus 03c274c319 Convert README to markdown language and rename to README.md 2017-11-09 10:57:24 -08:00
Matt Guthaus 0744cbcc60 Merge branch 'master' into dev 2017-11-09 09:11:26 -08:00
Matt Guthaus 05158f104b Removed unnecessary sram_tb.v file. 2017-10-17 15:51:31 -07:00
Matt Guthaus 225265f1dd Set theme jekyll-theme-minimal 2017-10-17 15:06:19 -07:00
Matt Guthaus be796967e2 Format BSD license. 2017-10-17 14:53:16 -07:00
mguthaus 5c10aebc0f Fix bug in multifinger ptx. Replace LEF file with new snapped layout. 2017-10-06 16:23:23 -07:00
Matt Guthaus 10a8531813 Fix new offset snap problems in wordline drive. Fix ptx multifinger pin bug. Add new add_center_rect function. 2017-10-06 15:30:15 -07:00
Matt Guthaus a9797d12ab Added pins to the ptx class. Modified pin class to do lazy write of GDS shapes to allow removal of pins. 2017-10-05 17:35:05 -07:00
Matt Guthaus b2043bef11 Fix small delay difference in unit test 21_hspice_delay_test. 2017-10-05 08:13:53 -07:00
Matt Guthaus 69e44c78d8 Upgrade version to 1.01 2017-10-04 20:18:30 -07:00
Matt Guthaus 59a0394c2b Update LEF files with modified blockages. 2017-10-04 20:17:30 -07:00
Matt Guthaus 788f3d9122 4-bank SRAMs are now working. 2017-10-04 18:05:45 -07:00
Matt Guthaus 21c77645d3 Remove LVS correspondence points for multibank in single bank. 2017-09-29 16:44:24 -07:00
Matt Guthaus e06e1691c8 Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
Matt Guthaus d29dd03373 SRAM single bank passing DRC/LVS. 2017-09-13 15:46:41 -07:00
Matt Guthaus 3ea003c367 Fix 1-way single bank LVS bug. Full SRAM still not functional. 8-way has DRC error. 2017-09-11 14:30:52 -07:00
Matt Guthaus d17711c394 Fixed several LVS errors. Bank passes LVS for 2-way and 4-way, but not 1-way or 8-way. 2017-08-24 16:22:14 -07:00
Matt Guthaus cf940fb15d Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
Matt Guthaus 7aa42f9a00 Added OSU to license 2017-08-15 13:44:13 -07:00
Matt Guthaus 4424ab64cb Update copyright holder 2017-08-15 08:27:19 -07:00
Matt Guthaus 857b997367 Modify LEF output to have all capital LAYER. Remove extra space before new lines. 2017-08-15 08:21:54 -07:00
Matt Guthaus 550eadfa82 Merge branch 'master' of https://github.com/mguthaus/OpenRAM 2017-08-15 06:10:50 -07:00
Matt Guthaus 1d10f9c734 Change license from GPL to BSD. 2017-08-15 06:10:32 -07:00
Matt Guthaus cb46fb0138 Merge branch 'master' of github.com:mguthaus/OpenRAM 2017-08-07 10:25:36 -07:00
Matt Guthaus d77216d6dd Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays. 2017-08-07 10:24:45 -07:00
Matt Guthaus 92df3ecf33 Replace periods in unique ptx names with an underscore. Fixes user bug with certain spice simulators. 2017-08-04 14:24:55 -07:00
Matt Guthaus 7c34a6404a Remove hierarchy that instantiates path and wire. Paths/wires are now added directly to a design. Removes a snap-to-grid bug when the instances are placed. Fixed add_wire/add_path in all uses. 2017-08-04 14:01:53 -07:00