17 Commits

Author	SHA1	Message	Date
Matt Guthaus	8d6a4c74e7	Merge branch 'dev' into control_fix	2019-08-10 13:07:30 -07:00
Hunter Nichols	3c44ce2df6	Replaced analytical characterization with graph implementation. Removed most analytical delay functions used by old chacterizer.	2019-08-08 02:33:51 -07:00
Matt Guthaus	d36f14b408	New control logic, netlist only working	2019-08-07 17:14:33 -07:00
Hunter Nichols	2efc0a3983	Merge branch 'dev' into analytical_cleanup	2019-08-06 14:51:30 -07:00
Hunter Nichols	24b1fa38a0	Added graph fixes to handmade multiport cells.	2019-07-30 20:31:32 -07:00
Hunter Nichols	dc46d07ca3	Removed unused code for input loads	2019-07-26 14:20:47 -07:00
Matt Guthaus	c8c4d05bba	Fix some regression fails.	2019-07-25 14:18:08 -07:00
Hunter Nichols	9696401f34	Added graph exclusions to replica column to reduce s_en paths.	2019-07-16 23:47:34 -07:00
mrg	8ca656959b	Change direction of RBL bitline pins	2019-07-16 15:09:46 -07:00
mrg	e550d6ff10	Port name maps between bank and replica array working.	2019-07-15 11:29:29 -07:00
mrg	2271946eef	Fix replica array pin names	2019-07-12 14:39:56 -07:00
mrg	043018e8ba	Functional tests working with new RBL.	2019-07-12 08:42:36 -07:00
mrg	0b13225913	Single banks working with new RBL	2019-07-11 14:47:27 -07:00
mrg	b841fd7ce3	Replica bitcell array with arbitrary RBLs working	2019-07-10 15:56:51 -07:00
mrg	9dab0be737	Single bank working with replica array.	2019-07-05 13:44:29 -07:00
mrg	b9d993c88b	Add dummy bitcell module. ... Modify bitcell logic to guess if bitcell is not "bitcell" No longer need to specify replica (and dummy) bitcell explicitly Add support for 1 or 2 port replica array.	2019-07-05 12:58:52 -07:00
mrg	4523a7b9f6	Replica bitcell array working	2019-06-19 16:03:21 -07:00