OpenRAM

mirror of https://github.com/VLSIDA/OpenRAM.git

Author	SHA1	Message	Date
mrg	5d33db0ee4	Add write driver to well connect list	2021-11-22 11:33:27 -08:00
mrg	2e846cb22f	Fix regexes for cells without well taps	2021-11-22 11:33:27 -08:00
mrg	acc9b2d223	Connect pwell and bulk when no tap	2021-11-22 11:33:27 -08:00
mrg	7d7ffe76e0	Debugging klayout for SCMOS and FreePDK45.	2021-11-22 11:33:27 -08:00