 Matt Guthaus
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c01f0f5274
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Merge branch 'dev' into fix_rbl_cell_connections
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2018-11-05 16:38:46 -08:00 |
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 Matt Guthaus
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3c5dc70ede
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Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd.
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2018-11-05 10:59:08 -08:00 |
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 Hunter Nichols
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f05865b307
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Fixed drc issues with replica bitline test.
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2018-11-02 17:16:41 -07:00 |
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Hunter Nichols
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9321f0461b
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Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r.
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2018-10-31 00:06:34 -07:00 |
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Hunter Nichols
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6efe0f56c2
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Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.
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2018-10-26 00:08:13 -07:00 |
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Hunter Nichols
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62439bdac6
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Fixed merge conflicts with sram.py
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2018-10-22 17:29:14 -07:00 |
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Hunter Nichols
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4f08062268
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Added custom 1rw+1r bitcell. Testing are currently failing.
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2018-10-22 17:02:21 -07:00 |
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Matt Guthaus
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ab7a83b7a5
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Remove old setup.tcl and edit one in tech dir
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2018-10-20 15:20:15 -07:00 |
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Matt Guthaus
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c0ffa9cc7b
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Clean up magic config file copying. Add warning for missing files.
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2018-10-05 08:36:12 -07:00 |
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Matt Guthaus
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b3fa6b9d52
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Make setup.tcl file a technology file
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2018-10-05 08:30:25 -07:00 |
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Matt Guthaus
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63d0523228
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Added scn4m_subm.
Added scn4m_subm files (instead of scn4me_subm).
Fixed missing cifoutput/cifinput in magic tech file and gds files.
Fixed incorrect M3/via3/M4 design rules.
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2018-09-13 12:53:35 -07:00 |
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