 Matt Guthaus
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6cdc870091
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Copy 1rw/1r cell to 1w/1r.
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2019-02-24 09:54:45 -08:00 |
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 Hunter Nichols
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80bc5b49c1
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Replaced bb layer with comment layer in 1rw,1r cell. Changed widths in replica cell.
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2018-11-14 11:00:37 -08:00 |
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Hunter Nichols
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8b6a28b6fd
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Changed scmos bitcell 1rw,1r to have same tx widths as pbitcell.
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2018-11-13 22:24:18 -08:00 |
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 Matt Guthaus
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c01f0f5274
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Merge branch 'dev' into fix_rbl_cell_connections
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2018-11-05 16:38:46 -08:00 |
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Matt Guthaus
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3c5dc70ede
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Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd.
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2018-11-05 10:59:08 -08:00 |
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Hunter Nichols
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f05865b307
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Fixed drc issues with replica bitline test.
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2018-11-02 17:16:41 -07:00 |
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Hunter Nichols
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9321f0461b
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Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r.
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2018-10-31 00:06:34 -07:00 |
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Hunter Nichols
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6efe0f56c2
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Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.
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2018-10-26 00:08:13 -07:00 |
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Matt Guthaus
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63d0523228
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Added scn4m_subm.
Added scn4m_subm files (instead of scn4me_subm).
Fixed missing cifoutput/cifinput in magic tech file and gds files.
Fixed incorrect M3/via3/M4 design rules.
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2018-09-13 12:53:35 -07:00 |
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