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OpenRAM
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309 Commits 4 Branches 63 Tags 78 MiB
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22 Commits

Author SHA1 Message Date
Matt Guthaus 490a70dee9 Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file. 2018-01-19 16:38:19 -08:00
Matt Guthaus abee235963 Rewrite the parameterized transistor and gate classes. 
Changes propagate through all designs.
All modules use instance and layout pins.
 2017-12-12 15:04:01 -08:00
Matt Guthaus 107cad15a1 Change layout function names to be consistent. 2017-11-30 12:01:04 -08:00
Matt Guthaus 0214cfb48e Fix single finger ptx bugs. 2017-11-30 11:56:40 -08:00
Matt Guthaus 1bcef7e3ee Prune ptx code. Change sizes to be relative to min size. 2017-11-29 12:31:00 -08:00
Matt Guthaus 7ff82a2aed Improved ptx code but removed internal active/poly positions. 2017-11-28 18:13:32 -08:00
Matt Guthaus 95f1a24f72 Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
Matt Guthaus 788f3d9122 4-bank SRAMs are now working. 2017-10-04 18:05:45 -07:00
Matt Guthaus e06e1691c8 Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
Matt Guthaus d29dd03373 SRAM single bank passing DRC/LVS. 2017-09-13 15:46:41 -07:00
Matt Guthaus 3ea003c367 Fix 1-way single bank LVS bug. Full SRAM still not functional. 8-way has DRC error. 2017-09-11 14:30:52 -07:00
Matt Guthaus d17711c394 Fixed several LVS errors. Bank passes LVS for 2-way and 4-way, but not 1-way or 8-way. 2017-08-24 16:22:14 -07:00
Matt Guthaus cf940fb15d Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
Matt Guthaus d77216d6dd Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays. 2017-08-07 10:24:45 -07:00
Matt Guthaus 20d8c0bc45 Improved characterizer. 2017-07-06 08:42:25 -07:00
mguthaus e92cb9ecef Removed array_type from ms_flop_array since it is extraneous code. 2017-07-03 12:08:50 -07:00
mguthaus f32912f07c Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity. 2017-06-02 11:11:57 -07:00
Matt Guthaus 34e180b901 Analytical delay model from Bin Wu. Unit test not passing. 2017-05-30 12:50:07 -07:00
Matt Guthaus 81ab1f1f82 Change layer order for add_wire 2016-11-17 14:05:50 -08:00
Bin wu 072a65a511 add rotate_scale function in vector and use it everywhere 2016-11-11 14:33:19 -08:00
Matt Guthaus e1c3d77a5d Removed import cell since cell is removed from simplified txt file 2016-11-09 12:20:52 -08:00
Matt Guthaus f48272bde6 RELEASE 1.0 2016-11-08 09:57:35 -08:00