8 Commits

Author	SHA1	Message	Date
mrg	e550d6ff10	Port name maps between bank and replica array working.	2019-07-15 11:29:29 -07:00
mrg	0b13225913	Single banks working with new RBL	2019-07-11 14:47:27 -07:00
mrg	b841fd7ce3	Replica bitcell array with arbitrary RBLs working	2019-07-10 15:56:51 -07:00
mrg	c0f9cdbc12	Create port address module	2019-07-05 09:03:52 -07:00
mrg	dd62269e0b	Some cleanup	2019-07-05 08:18:58 -07:00
Matt Guthaus	0cb86b8ba2	Exclude new precharge in graph build	2019-07-03 14:46:20 -07:00
mrg	bc4a3ee2b7	New port_data module works in SCMOS	2019-07-03 13:17:12 -07:00
mrg	244604fb0d	Data port module working by itself.	2019-07-02 15:35:53 -07:00