64 Commits

Author	SHA1	Message	Date
Matt Guthaus	9a4b2b4341	Revised LEF and Verilog generation. Does not read GDS for speed improvements.	2017-12-19 09:01:24 -08:00
mguthaus	09ca8ba17d	Improve output format. Rename option to be more sensible.	2017-11-22 15:57:29 -08:00
mguthaus	2eb9f5c6bc	Move verify into a module. Make characterizer a module. Move exe searching to modules.	2017-11-15 17:02:53 -08:00
Matt Guthaus	257cd62d25	Remove tools from tech file and have search order preference like spice.	2017-11-14 15:27:03 -08:00
Matt Guthaus	3e0f39cd8e	Skeleton code for indirect DRC/LVS/PEX tools.	2017-11-14 14:59:14 -08:00
Matt Guthaus	29c5ab48f0	Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output.	2017-11-14 13:24:14 -08:00
Matt Guthaus	95f1a24f72	Change default delay modeling to analytical. Add command-line option characterization by simulation (-c).	2017-11-09 11:13:44 -08:00
Matt Guthaus	8a821e13ac	Convert print to functional type call like Python 3. Perform error checking that requires Python >2.7 <3.0 for better error checking.	2017-06-12 15:02:48 -07:00
mguthaus	6e90bf0d6d	Enable output filename and path to be in config file. Command line will over-ride config file.	2017-06-12 14:37:15 -07:00
Matt Guthaus	51e4104624	Modify banner to output temp path	2016-11-15 10:14:04 -08:00
Matt Guthaus	eb57c6e7fd	Fix arg parsing order in openram.py	2016-11-15 09:36:15 -08:00
Matt Guthaus	cbc0f7c5d2	run_pex argument is now use_pex. Each unit test must RESET its options before assertions for consistent start state.	2016-11-15 09:03:16 -08:00
Matt Guthaus	9ea1a06244	Remove openram_temp at end of openram and unit tests.	2016-11-11 14:05:14 -08:00
Matt Guthaus	f48272bde6	RELEASE 1.0	2016-11-08 09:57:35 -08:00