 Jesse Cirimelli-Low
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4ea0fcd068
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support multi cell wide precharge cells
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2021-04-23 22:49:29 -07:00 |
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Jesse Cirimelli-Low
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e976c4043b
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Merge branch 'dev' into laptop_checkpoint
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2021-04-14 15:58:06 -07:00 |
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Jesse Cirimelli-Low
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2f1d7b879f
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make bank compatable with sky130
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2021-04-14 15:09:25 -07:00 |
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 mrg
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b6f3fbdd1f
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Use OPTS.precharge instead of hard coded precharge.
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2021-03-15 09:44:14 -07:00 |
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mrg
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db118beeba
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Zoom parameter should be optional in tech files.
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2021-03-02 13:38:09 -08:00 |
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mrg
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90cb9f581f
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Fixes to get hspice delay test to pass.
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2021-03-02 09:28:41 -08:00 |
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mrg
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fb953c19e8
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Remove option that causes errors and is unused.
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2021-03-01 16:36:27 -08:00 |
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mrg
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13bdae2e30
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Merge remote-tracking branch 'private/dev' into control-logic-pull
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2021-03-01 15:47:33 -08:00 |
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mrg
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049d3ffcaf
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Remove extra test file
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2021-03-01 15:25:39 -08:00 |
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mrg
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9e7c04a43a
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Merge lekez2005 changes WITHOUT control logic change.
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2021-03-01 15:19:30 -08:00 |
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mrg
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f31125645e
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2021-03-01 14:06:51 -08:00 |
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mrg
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4ab694033d
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Merge remote-tracking branch 'bvhoof/dev' into dev
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2021-03-01 12:16:26 -08:00 |
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mrg
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ae8926c5c2
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Merge remote-tracking branch 'private/dev' into dev
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2021-03-01 12:12:44 -08:00 |
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mrg
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5ab67214e5
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Make sure to add path when source and target
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2021-03-01 11:37:42 -08:00 |
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 Bob Vanhoof
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f5a9ab3b2c
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cleanup clutter
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2021-03-01 15:23:57 +01:00 |
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Bob Vanhoof
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fde8794282
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calibre pex modifications to run hierarchical pex
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2021-03-01 09:56:25 +01:00 |
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 ota2
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f6afef8d4a
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rbl_bl_delay_bar to rbl_bl_delay for write enable
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2021-02-27 19:30:37 -05:00 |
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ota2
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9d025604ff
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Simulate calibre extracted netlists without requiring extra layout ports
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2021-02-27 19:29:18 -05:00 |
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ota2
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9a2987ad07
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Add spectre simulator
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2021-02-27 19:25:00 -05:00 |
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ota2
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48bc47c686
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Set pin label size to use zoom factor from tech specifications
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2021-02-27 18:30:57 -05:00 |
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mrg
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0c2ed487d9
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Redundant check if pin contains another
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2021-02-26 11:16:19 -08:00 |
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mrg
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9f0ab0d081
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Route perimeter signals before power grid
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2021-02-26 11:14:39 -08:00 |
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mrg
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2a9b5db6d4
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Rewrite enclose grids to be cleaner
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2021-02-26 11:14:08 -08:00 |
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mrg
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013836bb3d
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PEP8 cleanup
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2021-02-23 13:33:14 -08:00 |
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mrg
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549112fcf8
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PEP8 cleanup
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2021-02-23 13:32:13 -08:00 |
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mrg
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1c6de4591d
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Remove vertical power pin vias.
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2021-02-23 13:32:00 -08:00 |
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 Hunter Nichols
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c308dd34a4
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Merge branch 'dev' into elmore_model_tuning
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2021-02-15 14:50:56 -08:00 |
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mrg
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33bc9a597c
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Remove dashes for Python module name warning.
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2021-02-15 08:19:08 -08:00 |
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mrg
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506daaec99
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Merge remote-tracking branch 'private/dev' into dev
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2021-02-13 23:52:18 -08:00 |
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mrg
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7610f23fc7
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Sub temp directory. Add github archive.
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2021-02-10 15:39:12 -08:00 |
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mrg
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b82b7aaf28
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PEP8 format
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2021-02-10 12:10:04 -08:00 |
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mrg
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c78d3a9cca
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Merge branch 'dev' into runner_test
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2021-02-10 11:17:35 -08:00 |
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mrg
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29c3d46be6
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Warn about threads forced to 1
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2021-02-10 10:23:06 -08:00 |
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jcirimel
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f2d4794cc6
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remove unused import
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2021-02-09 21:01:16 -08:00 |
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jcirimel
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b18e2eae8d
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remove debug lines and merge
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2021-02-09 20:53:23 -08:00 |
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jcirimel
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dbe8a7f1af
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fix pwell pin shape bug
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2021-02-09 20:51:50 -08:00 |
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Bob Vanhoof
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d14a68847e
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added cell label checker and cell labels to the freepdk technology
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2021-02-09 13:09:26 +01:00 |
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Bob Vanhoof
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3dfc039f6f
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add technology option passtrough in test 30
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2021-02-09 09:32:35 +01:00 |
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mrg
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b83d93cc9a
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GitHub Actions CI flow.
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2021-02-08 15:46:02 -08:00 |
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mrg
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e043aaffb3
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Don't print DRC/LVS/PEX run stats in regress.py
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2021-02-03 15:17:28 -08:00 |
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mrg
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19e99d1c7b
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Enable parallel regression testing.
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2021-02-03 14:19:11 -08:00 |
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Hunter Nichols
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df8d59f32e
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Merge branch 'dev' into automated_analytical_model
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2021-02-01 01:49:45 -08:00 |
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Hunter Nichols
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7bed5bdd1c
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Added option for model to specify regression model data path.
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2021-01-25 14:24:54 -08:00 |
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mrg
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bc8fd4a882
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Merge branch 'supply_router' into dev
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2021-01-25 11:01:48 -08:00 |
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Matt Guthaus
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eebc2a93b6
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Remove redundant pins when adding each pin
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2021-01-25 09:36:27 -08:00 |
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Matt Guthaus
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30fc81a1f0
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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Hunter Nichols
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e26e17c53f
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Added option to specify exact corners for characterization in config file
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2021-01-22 00:50:28 -08:00 |
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mrg
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db142bcd5a
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Rename pins to original names
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2021-01-21 15:22:54 -08:00 |
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Hunter Nichols
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d1b240dfb5
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Added nom_voltage, etc back but changed values to replicate the operating conditions. Readded nom values back in golden files.
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2021-01-21 13:52:55 -08:00 |
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Hunter Nichols
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31ad1963f6
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Removed nominal pvt corners from golden lib files.
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2021-01-21 12:47:18 -08:00 |
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