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Author	SHA1	Message	Date
Jesse Cirimelli-Low	4ea0fcd068	support multi cell wide precharge cells	2021-04-23 22:49:29 -07:00
Jesse Cirimelli-Low	e976c4043b	Merge branch 'dev' into laptop_checkpoint	2021-04-14 15:58:06 -07:00
Jesse Cirimelli-Low	2f1d7b879f	make bank compatable with sky130	2021-04-14 15:09:25 -07:00
mrg	b6f3fbdd1f	Use OPTS.precharge instead of hard coded precharge.	2021-03-15 09:44:14 -07:00
mrg	db118beeba	Zoom parameter should be optional in tech files.	2021-03-02 13:38:09 -08:00
mrg	da3a100301	Try new wildcard for archive path.	2021-03-02 09:28:59 -08:00
mrg	90cb9f581f	Fixes to get hspice delay test to pass.	2021-03-02 09:28:41 -08:00
mrg	fb953c19e8	Remove option that causes errors and is unused.	2021-03-01 16:36:27 -08:00
mrg	13bdae2e30	Merge remote-tracking branch 'private/dev' into control-logic-pull	2021-03-01 15:47:33 -08:00
mrg	049d3ffcaf	Remove extra test file	2021-03-01 15:25:39 -08:00
mrg	9e7c04a43a	Merge lekez2005 changes WITHOUT control logic change.	2021-03-01 15:19:30 -08:00
mrg	1614dc140d	Remove tab	2021-03-01 14:59:49 -08:00
mrg	96faf06b7c	Each job must checkout with multiple runners	2021-03-01 14:58:55 -08:00
mrg	01094ae4f0	Don't upload coverage artifacts	2021-03-01 14:56:56 -08:00
mrg	f31125645e	Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev	2021-03-01 14:06:51 -08:00
mrg	4ab694033d	Merge remote-tracking branch 'bvhoof/dev' into dev	2021-03-01 12:16:26 -08:00
mrg	ae8926c5c2	Merge remote-tracking branch 'private/dev' into dev	2021-03-01 12:12:44 -08:00
mrg	bedd1b3d15	Don't need to cleanup as checkout does it.	2021-03-01 11:40:58 -08:00
mrg	5ab67214e5	Make sure to add path when source and target	2021-03-01 11:37:42 -08:00
mrg	7c15773e17	Only remove temp dirs, erase coverage	2021-03-01 10:51:09 -08:00
mrg	27c197026f	Only remove temp dirs, erase coverage	2021-03-01 10:50:37 -08:00
mrg	5b6bfce7e0	Add steps	2021-03-01 10:37:33 -08:00
mrg	c6baef1c59	Remove tabs	2021-03-01 10:34:46 -08:00
mrg	0ba1ceff6a	Separate checkout step	2021-03-01 10:33:57 -08:00
mrg	f7d66b7d2c	Update workflow syntax	2021-03-01 10:31:32 -08:00
mrg	7355fc91f8	Update workflow syntax	2021-03-01 10:28:47 -08:00
mrg	0556b931a9	Update workflow syntax	2021-03-01 10:27:56 -08:00
mrg	ec783f58b8	Update workflow syntax	2021-03-01 10:22:30 -08:00
mrg	26eed77de0	Update workflow syntax	2021-03-01 10:20:48 -08:00
mrg	59915962a0	Update workflow syntax	2021-03-01 10:19:36 -08:00
mrg	ab0b9ca37b	Fix syntax error in workflow	2021-03-01 10:15:33 -08:00
mrg	ef78ad7249	Upload workflow	2021-03-01 10:12:37 -08:00
Bob Vanhoof	f5a9ab3b2c	cleanup clutter	2021-03-01 15:23:57 +01:00
Bob Vanhoof	fde8794282	calibre pex modifications to run hierarchical pex	2021-03-01 09:56:25 +01:00
ota2	f6afef8d4a	rbl_bl_delay_bar to rbl_bl_delay for write enable	2021-02-27 19:30:37 -05:00
ota2	9d025604ff	Simulate calibre extracted netlists without requiring extra layout ports	2021-02-27 19:29:18 -05:00
ota2	9a2987ad07	Add spectre simulator	2021-02-27 19:25:00 -05:00
ota2	48bc47c686	Set pin label size to use zoom factor from tech specifications	2021-02-27 18:30:57 -05:00
ota2	15e57d89ca	fix end subckt typo	2021-02-27 18:28:07 -05:00
ota2	8403749fec	Add Q and Qbar labels	2021-02-27 18:27:08 -05:00
mrg	a57a443a4c	Change coverage report location	2021-02-26 16:31:41 -08:00
mrg	dc3c293575	Add temp workspace path	2021-02-26 16:17:45 -08:00
mrg	0c2ed487d9	Redundant check if pin contains another	2021-02-26 11:16:19 -08:00
mrg	9f0ab0d081	Route perimeter signals before power grid	2021-02-26 11:14:39 -08:00
mrg	2a9b5db6d4	Rewrite enclose grids to be cleaner	2021-02-26 11:14:08 -08:00
mrg	013836bb3d	PEP8 cleanup	2021-02-23 13:33:14 -08:00
mrg	549112fcf8	PEP8 cleanup	2021-02-23 13:32:13 -08:00
mrg	1c6de4591d	Remove vertical power pin vias.	2021-02-23 13:32:00 -08:00
Hunter Nichols	c308dd34a4	Merge branch 'dev' into elmore_model_tuning	2021-02-15 14:50:56 -08:00
mrg	c3156be7b1	Change from 32 to 48 threads	2021-02-15 12:02:22 -08:00