16 Commits

Author	SHA1	Message	Date
mrg	29ac541b28	Refactor dynamic cell name to utilize base class	2020-11-03 13:18:46 -08:00
mrg	da721a677d	Remove EOL whitespace globally	2020-11-03 06:29:17 -08:00
mrg	f9787eb878	Use bitcell_base for all bitcells. Fix missing setup_bitcell call	2020-11-02 17:00:15 -08:00
mrg	fa89b73ef8	PR from mithro + other changable GDS file names	2020-11-02 16:00:16 -08:00
Bastian Koppelmann	87b5a48f9e	bitcell: Remove hardcoded signal pins ... use names provided by the tech file, which can be overriden by the technology. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>	2020-02-12 15:37:51 +01:00
Hunter Nichols	fc1cba099c	Made all cin function relate to farads and all input_load relate to relative units.	2019-08-08 01:57:04 -07:00
Hunter Nichols	6860d3258e	Added graph functions to compute analytical delay based on graph path.	2019-08-07 01:50:48 -07:00
Hunter Nichols	24b1fa38a0	Added graph fixes to handmade multiport cells.	2019-07-30 20:31:32 -07:00
Hunter Nichols	4e08e2da87	Merged and fixed conflicts with dev	2019-06-25 16:55:50 -07:00
Matt Guthaus	a234b0af88	Fix space before comment	2019-06-14 08:43:41 -07:00
Hunter Nichols	d8617acff2	Merged with dev	2019-05-15 18:48:00 -07:00
Hunter Nichols	d54074d68e	Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.	2019-05-07 00:52:27 -07:00
Matt Guthaus	0f03553689	Update copyright to correct years.	2019-05-06 06:50:15 -07:00
Matt Guthaus	3f9a987e51	Update copyright. Add header to all OpenRAM files.	2019-04-26 12:33:53 -07:00
Hunter Nichols	e292767166	Added graph creation and functions in base class and lower level modules.	2019-04-24 14:23:22 -07:00
Matt Guthaus	6cdc870091	Copy 1rw/1r cell to 1w/1r.	2019-02-24 09:54:45 -08:00