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OpenRAM
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4,214 Commits 4 Branches 63 Tags 78 MiB
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56 Commits

Author SHA1 Message Date
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
Eren Dogan e3fe8c3229 Remove line ending whitespace 2022-07-22 19:52:38 +03:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
mrg 8217a84165 Uniquify overlap points during segment overlap computation. 2022-05-17 13:31:23 -07:00
mrg 4be075e586 Overlap length can include a rectangle overlap. 2022-05-16 14:57:32 -07:00
mrg b6c3580e24 Fix width of replica routes. Don't enclose pins if they overlap sufficiently. 2022-05-09 11:44:46 -07:00
mrg b1bb9151c4 Reimplement off grid pins. 
Long pins aren't accessed on end pins anymore.
Fix problem with multiple non-enclosed space causing blockages.
Add partial pin offgrid enclosure algorithm.
 2022-05-02 15:43:14 -07:00
Jesse Cirimelli-Low b5daa51a6c don't use hard coded purpose numbers 2021-07-01 17:31:01 -07:00
Jesse Cirimelli-Low c9b3f4772e fix bias correspondence points 2021-06-30 05:21:39 -07:00
mrg f6587badad Improve supply routing for ring and side pins 2021-05-28 10:58:30 -07:00
mrg f45efe3db6 Abstracted LEF added. Params for array wordline layers. 2021-04-21 11:04:01 -07:00
mrg 41226087ba Use separate mXp pin layer if it exists 2021-04-14 13:55:21 -07:00
mrg db118beeba Zoom parameter should be optional in tech files. 2021-03-02 13:38:09 -08:00
ota2 48bc47c686 Set pin label size to use zoom factor from tech specifications 2021-02-27 18:30:57 -05:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg 9a3776e758 Use default zoom for text 2020-12-14 14:18:00 -08:00
mrg d542b7dd76 Add separate box for pins if it has its own purpose 2020-12-08 10:31:57 -08:00
mrg d4c4658c77 Clean up invalid routing layer error message 2020-11-12 09:43:08 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
Matt Guthaus e97644c424 Only do reverse lookup on valid interconnect layers since layer numbers can be shared. 2020-06-29 14:42:24 -07:00
mrg 7ad2d54a69 Add pin and label purposes 2020-06-11 11:54:51 -07:00
Joey Kunzler d6987ac584 added purposes to addText(), removed reference to specific tech from gdsMill 2020-02-19 16:26:52 -08:00
Matt Guthaus e62beae805 Merge branch 'tech_migration' into dev 2020-01-25 12:03:56 -08:00
mrg 306740f0f3 Add empty minarea function 2020-01-16 19:27:59 +00:00
Bastian Koppelmann 7ff5121d8c base/pin_layout: Implement hash cache 
the hash value only depends of the properties 'rect' and 'layer' so we
only compute the hash if those values are changed. Otherwise we just
return the precomputed value. This gives us a major speedup (~10x) if
the hash is used as a key in a dict.

During the grouping of pins in analyze_pins() this gives the best
improvements. For example for FreePDK45 with num_bits=8, num_words=256

Improved
**** Analyzing pins: 20.9 seconds
** Routing: 293.8 seconds
** SRAM creation: 349.8 seconds

Non-improved
**** Analyzing pins: 267.9 seconds
** Routing: 537.5 seconds
** SRAM creation: 592.9 seconds

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-03 11:39:59 +01:00
Bastian Koppelmann 14e8a26246 base/pin_layout: Make rect and layer properties 
only rect and layer are used to compute the hash for a pin. Having
those as properties allows us to cache the hash value and only update it
if either rect or layer are written.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-03 11:33:34 +01:00
Matt Guthaus 69bb245f28 Updates to gdsMill/tech layers 
Create active and poly contact types.
Define standard cell boundary option.
DataType and PurposeLayer are the same. Text must have type 0.
Remove vector from vlsiLayout. More debug in reader.
 2019-12-04 16:12:53 -08:00
Matt Guthaus 909321326d Ignore unused layers 2019-11-26 13:21:29 -08:00
Matthew Guthaus 131f4bda4a Add layer-purpose GDS support. Various PEP8 fixes. 2019-11-14 18:17:20 +00:00
Matthew Guthaus 32f1cde897 PEP8 formatting 2019-11-07 16:48:37 +00:00
Matt Guthaus 38213d998f Add separate layer and purpose pairs to tech layers. 2019-10-25 10:03:25 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus 126d4a8d10 Fix instersection bug. Improve primary and secondary pin algo. 2018-12-04 16:53:04 -08:00
Matt Guthaus b8299565eb Use grid furthest from blockages when blocked pin. Enclose multiple connectors. 2018-11-19 17:32:55 -08:00
Matt Guthaus 20d4e390f6 Add bounding box of connector for when there are multiple connectors 2018-11-19 15:45:07 -08:00
Matt Guthaus 6a7d721562 Add new bbox routine for pin enclosures 2018-11-19 09:28:29 -08:00
Matt Guthaus de61630962 Expand blocked pins to neighbor grid cells. 2018-11-09 14:25:10 -08:00
Matt Guthaus b24c8a42a1 Remove redundant pins in pin_group constructor. Clean up some code and comments. 2018-11-01 11:31:24 -07:00
Matt Guthaus c511d886bf Added new enclosure connector algorithm using edge sorting. 2018-10-31 15:35:39 -07:00
Matt Guthaus fc45242ccb Allow contains to contain copy. Add connectors when pin doesn't overlap grids. 2018-10-30 17:41:29 -07:00
Matt Guthaus 6990773ea1 Add error check requiring non-zero area pin layouts. 2018-10-29 10:32:42 -07:00
Matt Guthaus 7d74d34c53 Fix pin_layout contains bug 2018-10-26 10:40:43 -07:00
Matt Guthaus 94e5050513 Move overlap functions to pin_layout 2018-10-24 16:13:07 -07:00
Matt Guthaus ce8c2d983d Update all drc usages to call function type 2018-10-12 14:37:51 -07:00
Matt Guthaus 6bbf66d55b Rewrote pin enclosure code to better address off grid pins. 
Include only maximal pin enclosure shapes.
Add smallest area connector for off grid pins.
Fix decoder to use add_power_pin code.
Change permissions.
 2018-10-10 15:15:58 -07:00
Matt Guthaus 87502374c5 DRC clean supply grid routing on control logic. 2018-09-20 16:00:13 -07:00
Matt Guthaus 8d2804b9cb Supply router working except: 
Off grid pins. Some pins do now span enough of the routing track and must be patched.
  Route track width. Instead of minimum width route, it should be the track width.
 2018-09-18 12:57:39 -07:00