OpenRAM

Commit Graph

Author	SHA1	Message	Date
Matt Guthaus	7cca6b4f69	Add back scn3me_subm support Add back scn3me_subm tech files Update cells to be DRC clean with rule 5.5.b Allow magic for FreePDK45 but not debugged. Revert to older Magic tech file for SCN3ME_SUBM	2019-06-03 15:27:37 -07:00
Matt Guthaus	1a54fd0d1c	Remove scn3me_subm since it does not have 4 metal layers	2019-03-11 14:20:02 -07:00
Matt Guthaus	4fc9278b73	Convert bounding box layer for SCMOS to bb, gds layer 63.	2018-09-04 13:05:21 -07:00
Michael Timothy Grimes	766042fe69	changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit	2018-05-22 14:16:51 -07:00
Matt Guthaus	a0bf5345f8	Mostly working for 1 bank.	2018-03-23 08:14:26 -07:00
Matt Guthaus	6f8744712d	Add extra pwc to 6T SCMOS cell.	2018-02-05 14:44:15 -08:00
Matt Guthaus	58da8af619	Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array.	2018-01-31 10:04:28 -08:00
Matt Guthaus	1dc7752429	Fix 6T and replica cell contact spacing issues with Magic DRC. DRC/LVS passing for all parameterized gates. Magic and GDS match for SCMOS rules again.	2018-01-26 12:39:00 -08:00
Matt Guthaus	fb2ed1d46c	Add wells to fix DRC errors in SCMOS library cells.	2018-01-22 16:28:20 -08:00
Matt Guthaus	e06e1691c8	Two bank SRAMs working in both technologies.	2017-09-29 16:22:13 -07:00
Matt Guthaus	cf940fb15d	Development version of new pin data structure. Tests pass LVS/DRC except for bank level.	2017-08-23 15:02:15 -07:00
Matt Guthaus	f48272bde6	RELEASE 1.0	2016-11-08 09:57:35 -08:00

12 Commits