19 Commits

Author	SHA1	Message	Date
mole99	85e242fa27	Add gf180mcu ROM example	2024-02-03 11:31:58 +01:00
Jesse Cirimelli-Low	788d7e5474	fix VPB/VNB pins not being found	2023-10-31 18:07:35 -07:00
Sam Crow	f1d91efebd	fix single port by using existing custom modules	2023-03-03 14:17:57 -08:00
mrg	1db9881ce7	Add sky130 corners to tech file.	2023-03-01 09:26:16 -08:00
Eren Dogan	e5fc25da6f	Update copyright year	2023-01-28 22:56:27 -08:00
Eren Dogan	96e57507bf	Add copyright check to code format test	2022-11-30 14:50:43 -08:00
Eren Dogan	fccdc3c45b	Use library imports globally	2022-11-27 13:01:20 -08:00
Jesse Cirimelli-Low	3b02a8846d	sky130 rba passing :)	2022-09-12 16:07:00 -07:00
Jesse Cirimelli-Low	11fa0777e8	add flatglob to tech file; sky130 replica col lvs working	2022-08-22 15:30:11 -07:00
mrg	d92c7a634d	Use packages for imports. ... Must set PYTHONPATH to include OPENRAM_HOME now. Reorganizes subdirs as packages. Rewrites unit tests to use packages. Update README.md with instructions, dependencies etc. Update sky130 module imports. Change tech specific package from modules to custom.	2022-07-13 15:55:57 -07:00
Jesse Cirimelli-Low	98fe4c74a4	colend fixes in progress	2022-06-15 22:34:21 -07:00
mrg	25fa0a8de3	Fix missing cell syntax error.	2022-05-19 14:53:17 -07:00
mrg	bdd334bce9	Add layer and directions to pbitcell	2022-05-16 16:11:13 -07:00
mrg	64f2f90664	Rework replica_bitcell_array supplies ... Uses layer and direction preferences in tech file. Places straps on left/right or top/bottom.	2022-04-19 08:50:11 -07:00
Jesse Cirimelli-Low	8d9166a01b	only rba lvs errors is colend body extraction	2021-12-29 12:43:02 -08:00
Jesse Cirimelli-Low	9e85d17fbe	merge rbc lvs fixes	2021-12-23 21:21:10 -08:00
mrg	02364c6cdf	Add klayout option in config. No tool specific LVS libs	2021-12-17 10:29:17 -08:00
Jesse Cirimelli-Low	8879820af4	replica col lvs fix	2021-12-15 14:19:52 -08:00
mrg	fa2232fc11	Initial commit of sky130 config files	2021-10-04 15:16:28 -07:00