OpenRAM

Author	SHA1	Message	Date
mrg	5285468380	All bitcells need a vdd/gnd pin	2020-06-28 15:09:47 -07:00
mrg	051c8d8697	Only add bitcells to dummy and replica rows and columns (the perimeter)	2020-06-28 14:47:54 -07:00
mrg	f84ee04fa9	Single bank passing. Parameterized gate column mux of dff height. End-cap only supply option instead of no vdd in bitcell.	2020-06-25 14:03:59 -07:00
mrg	443b8fbe23	Change s8 to sky130	2020-06-12 14:23:26 -07:00
Joey Kunzler	7505fa5aef	update for end caps	2020-05-27 20:03:11 -07:00
mrg	dd73afc983	Changes to allow decoder height to be a 2x multiple of bitcell height. Convert to use li layer in pgates. Fix multifinger devices with li layers. Simplify wordline driver input routing. Fix power pin direction option update. PEP8 cleanup Changes to simplify metal preferred directions and pitches. Split of control logic tests.	2020-05-10 06:56:22 -07:00
Joey Kunzler	d7529ce526	Vdd/gnd via stacks now use perferred directions, added cell property to override	2020-03-04 17:05:19 -08:00
Bastian Koppelmann	f6302caeac	replica_bitcell_array: Connect bitcells based on bitcell bl/br/wl names this allows us to override the bl/br/wl names of each bitcell. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>	2020-02-12 15:37:47 +01:00
mrg	79391b84da	Cleanup and rename vias.	2020-01-30 01:45:33 +00:00