diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py
index b5534226..b3f6983f 100644
--- a/compiler/sram/sram_1bank.py
+++ b/compiler/sram/sram_1bank.py
@@ -259,7 +259,8 @@ class sram_1bank(sram_base):
             self.route_col_addr_dff()
         
         self.route_data_dff()
-        self.route_wmask_dff()
+        if self.write_size is not None:
+            self.route_wmask_dff()
 
     def route_clk(self):
         """ Route the clock network """
diff --git a/compiler/tests/10_write_driver_array_wmask_test.py b/compiler/tests/10_write_driver_array_wmask_test.py
index 47a3940b..d09286b5 100644
--- a/compiler/tests/10_write_driver_array_wmask_test.py
+++ b/compiler/tests/10_write_driver_array_wmask_test.py
@@ -20,7 +20,7 @@ import debug
 class write_driver_test(openram_test):
 
     def runTest(self):
-        globals.init("config_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         # check write driver array for single port
         debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4")