mirror of https://github.com/VLSIDA/OpenRAM.git
remove superfluous imports from multiport test
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@ -24,8 +24,6 @@ class control_logic_delay_test(openram_test):
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def runTest(self):
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def runTest(self):
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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globals.init_openram(config_file)
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globals.init_openram(config_file)
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import control_logic_delay
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import tech
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# check control logic for multi-port
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# check control logic for multi-port
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OPTS.bitcell = "pbitcell"
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OPTS.bitcell = "pbitcell"
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