diff --git a/compiler/tests/16_control_logic_delay_multiport_test.py b/compiler/tests/16_control_logic_delay_multiport_test.py
index 7ea40309..590b2d7c 100755
--- a/compiler/tests/16_control_logic_delay_multiport_test.py
+++ b/compiler/tests/16_control_logic_delay_multiport_test.py
@@ -24,8 +24,6 @@ class control_logic_delay_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
-        import control_logic_delay
-        import tech
 
         # check control logic for multi-port
         OPTS.bitcell = "pbitcell"