remove superfluous imports from multiport test

2026-09-04 08:44:12 +02:00 · 2022-07-22 13:12:03 -07:00
parent b82213caff
commit f01e73328d
1 changed files with 0 additions and 2 deletions
@@ -24,8 +24,6 @@ class control_logic_delay_test(openram_test):
    def runTest(self):
        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
        globals.init_openram(config_file)
-        import control_logic_delay
-        import tech

        # check control logic for multi-port
        OPTS.bitcell = "pbitcell"