exclude rbl connection in sram base for delay control logic

2026-08-29 01:24:39 +02:00 · 2022-07-21 19:35:01 -07:00
parent 7d4b718344
commit ef2c9fe296
1 changed files with 2 additions and 1 deletions
@@ -717,7 +717,8 @@ class sram_base(design, verilog, lef):
            if port in self.readwrite_ports:
                temp.append("web{}".format(port))
            temp.append("clk{}".format(port))
-            temp.append("rbl_bl{}".format(port))
+            if OPTS.control_logic != "control_logic_delay":
+                temp.append("rbl_bl{}".format(port))

            # Outputs
            if port in self.read_ports: