diff --git a/compiler/modules/sram_base.py b/compiler/modules/sram_base.py
index 722a649d..21f068fc 100644
--- a/compiler/modules/sram_base.py
+++ b/compiler/modules/sram_base.py
@@ -717,7 +717,8 @@ class sram_base(design, verilog, lef):
             if port in self.readwrite_ports:
                 temp.append("web{}".format(port))
             temp.append("clk{}".format(port))
-            temp.append("rbl_bl{}".format(port))
+            if OPTS.control_logic != "control_logic_delay":
+                temp.append("rbl_bl{}".format(port))
 
             # Outputs
             if port in self.read_ports: